1) Field of the Invention
This invention relates generally to the fabrication of insulating layers for semiconductor devices and particularly to methods for forming interlevel dielectric (ILD) layers having contact holes and rapid thermal anneals.
2) Description of the Prior Art
Integrated circuits are chemically and physically integrated onto a substrate, such as a silicon substrate, by patterning conductive regions in the substrate and by patterning conductive and insulation layers over the substrate. The various conductive and insulation layer create uneven surfaces on a semiconductor structure.
For high density devices of submicron size it is essential to start with a flat wafer and to maintain a flat planarized surface at various fabrication steps. If the process steps for device fabrication are performed on a semiconductor structure surface that is not uniform and planarized, various problems can occur which may result in a large number or inoperable devices.
Interlevel dielectric (ILD) layers 24 are formed between conductive layers (e.g., metal or polysilicon) in a semiconductor device or between conductive lines formed from the same conductive layer (in the same level). Contact holes are formed through the ILD layers to make electrical contact with conductive layers and device regions there below. As shown in FIG. 4, the inventor has encountered a major problem with submicron contacts and contact holes in ILD layers. FIG. 4 shows a semiconductor structure 12 (including a substrate or underlying layer 10) with the following layers overlying: insulating layers 16 (e.g., USG), 20 (e.g., BPTEOS ) and an ILD layer 24 (e.g., PETEOS), contact hole 30A and conductive contact 34. The inventor has performed various experiments and diagnostics to determine that the ILD layer 24 is shrinking and shifting thereby making the contacts skewed 33 (contact oblique problem 33). This skewing 33 of contact reduces yields and lower device reliability.
The inventor has determined that this skewing contact problem (contact oblique problem) occurs after heating (annealing) a PE-TEOS ILD layer 24 having a contact hole 30A. The contact oblique problem 33 often occurs when the PE-TEOS ILD layer 24 has a thickness gradient (e.g., as shown in FIG. 4 from the left (thin ILD layer) to the right (thicker ILD layer). The composition of the layer (e.g., 20) underlying the PE-TEOS ILD layer 24 can make the contact oblique problem worse. For example, the inventor found that an underlying layer 20 composed of BPTEOS often worsens the contact oblique problem. The thickness variations in the ILD layer 24 are commonly created by planarization processes such as chemical-mechanical polish and etch back processes.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,618,381 (Doan) shows a CMP polishing method. U.S. Pat. No. 5,395,790 (Lur) shows a method of forming trenches in the isolation area followed by an anneal which relieves the stress. U.S. Pat. No. 5,296,411 (Gardner) shows a N.sub.2 anneal for a tunnel oxide. U.S. Pat. No. 5,635,425 (Chen) shows a N.sub.2 Plasma treatment for a TEOS layer.
However, the problem of interlevel dielectric layers shifting and causing contact oblique problems requires a cost-effective solution.